The entire disclosure of a Japanese Patent Application No. 2001-313410 filed on Oct. 11, 2001 including its specification, claims, drawings and summary are incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same, and in particular to a technology for patterning electrical wiring, etc.
2. Description of Prior Art
FIG. 5A through FIG. 6B are sectional views of applicable parts to describe a prior art method for forming electrical wiring of a semiconductor device using the photolithography method. In the prior art method, first, as shown in FIG. 5A, a semiconductor substrate 1 covered by a wiring layer 3 is prepared.
Next, as shown in FIG. 5B, photoresist 7a of a prescribed pattern is formed on the wiring layer 3, and etching is carried out by using the photoresist 7a as a mask, wherein the wiring layer 3 is patterned as shown in FIG. 6A. After that, by removing the photoresist 7a, it is possible to form wiring 3a of a desired pattern as shown in FIG. 6B.
However, in the above-described prior art method of forming wiring, there are the following problems. In order to increase integration of a semiconductor device while securing a permissible current value of the wiring 3a (that is, without increasing the electric resistance value of the wiring 3a), the thickness a of the wiring 3a shown in FIG. 6B is made thick, and simultaneously the width b of the wiring 3a and its array pitch may be made narrow. If so, it is possible to decrease the plane projection area of the wiring portion without decreasing the sectional area of the wiring 3a. 
However, in order to make the thickness a of the wiring 3a thick, the thickness of the photoresist 7a must be made thick because, when etching the wiring layer 3, the thickness and width of the photoresist 7a are decreased by the etching. That is, it is necessary to provide a photoresist 7a having a thickness matched to the thickness a of the wiring 3a (in other words, the etching time).
However, if the thickness of the photoresist 7a is made thick, the following problems occur. First, since the time of exposure to form a photoresist 7a becomes long, the photoresist 7a is liable to be deformed by the exposure. Also, many portions where focusing can be scarcely secured in the thickness direction of the photoresist are obliged to occur, resulting in a lowering in the resolution power when exposed. Further, foaming and/or deformation are liable to occur in the photoresist 7a by baking, which is carried out after development, whereby the photoresist 7a is not shaped as per design, resulting in irregular shapes of the wiring 3a. 
In addition, when removing the photoresist 7a after etching, some of the photoresist 7a is likely to remain.
Therefore, such a problem occurs, for which reliability in actions and operations of a semiconductor device thus produced may be lowered.
It is therefore an object of the invention to provide a semiconductor device and a method for producing the same, which are able to solve these problems, and by which almost no irregular shape is brought about in layers to be patterned even in a case of layers to be patterned such as wiring layers required to be patterned over a long etching time. Further, it is another object of the invention to provide a semiconductor device having high reliability in actions and operations and a method for producing the same.
A method for producing a semiconductor device according to the invention comprises the steps of: preparing a semiconductor substrate on which a layer to be patterned is formed; forming an auxiliary mask layer so that the same layer covers said layer to be patterned; forming photoresist of a prescribed pattern so that the photoresist is brought into contact with the auxiliary mask layer on the upper part of the auxiliary mask layer; patterning the auxiliary mask layer by carrying out the first etching for which the etching speed with respect to the photoresist is lower than that with respect to the auxiliary mask layer using the photoresist as a mask, and forming a auxiliary mask; and patterning the layer to be patterned by carrying out the second etching for which the etching speed with respect to the photo resist is lower than that with respect to the layer to be patterned, and is higher than the etching speed with respect to the auxiliary mask, using the auxiliary mask, which is formed through the first etching, and the remaining photoresist as masks.
A semiconductor device according to the invention comprises wiring of a prescribed pattern, which is provided on a semiconductor substrate, and an insulation membrane, which is an insulation membrane utilized as a mask for patterning the wiring, provided in contact with the wiring on the wiring and having the same pattern as that of the wiring.
A semiconductor device according to the invention is formed by: preparing a semiconductor substrate on which a layer to be patterned is formed; forming an auxiliary mask layer so that the same layer covers said layer to be patterned; forming photoresist of a prescribed pattern so that the photoresist is brought into contact with the auxiliary mask layer on the upper part of the auxiliary mask layer; patterning the auxiliary mask layer by carrying out the first etching for which the etching speed with respect to the photoresist is lower than that with respect to the auxiliary mask layer using the photoresist as a mask, and forming a auxiliary mask; and patterning the layer to be patterned by carrying out the second etching for which the etching speed with respect to the photoresist is lower than that with respect to the layer to be patterned, and is higher than the etching speed with respect to the auxiliary mask, using the auxiliary mask, which is formed through the first etching, and the remaining photoresist as masks.
While the features of the present invention are broadly described above, the constitution and contents of the invention, together with the object and features, will become more apparent in the following disclosure in reference to the appended drawings.